1. Field
Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern.
2. Description of the Related Art
A metal-oxide-semiconductor (MOS) transistor may include a gate pattern formed on a semiconductor substrate and source/drain regions formed in a portion of the semiconductor substrate near lower portions of both sidewalls of the gate pattern. The gate pattern may include a gate insulation layer formed on the semiconductor substrate, a gate electrode layer formed on the gate insulation layer and a gate hard mask layer formed on the gate electrode layer. A gate spacer layer may be formed on the sidewalls of the gate pattern. In a MOS transistor, when a threshold voltage is applied to a gate electrode thereof, a channel layer may be formed near a surface of a semiconductor substrate which may be a lower portion of a gate pattern. When a drain voltage is applied, current may flow between a source region and a drain region, according to the carrier movement and the MOS transistor may operate.
In the conventional art, a silicon substrate in a lower portion of both sidewalls of the gate pattern may be selectively etched using an etching solution and an epitaxial layer, including germanium (Ge), may be formed in the etched portion, thereby inducing a compressive stress in the channel region. According to the conventional art, because the silicon substrate of the lower portions of the sidewalls of the gate pattern may be etched in a wet or dry etching apparatus, and then an epitaxial growth process for the etched portion may be performed in a chemical vapor deposition (CVD) apparatus, an intermediate treatment process (e.g., a washing process) for the etched portion may be performed before the epitaxial growth process, resulting in increased processing time.